Processor architectures conventionally utilize a hierarchy of cache when executing instructions or processing data. Typically, lower level caches, such as L0 or L1 cache, are implemented as relatively low storage capacity but relatively fast caches, whereas higher level caches, such as L2 cache, are implemented as relatively high storage capacity but relatively slow caches. When an instruction pipeline or data pipeline requires instructions or data for processing, each cache typically is checked in a hierarchical sequence until the instructions or data are found or until it becomes necessary to go to system memory to obtain the sought-for instructions or data. As cache accesses typically have a significantly smaller time penalty than external memory accesses, this hierarchical cache approach has the advantage of minimizing processing delays when the sought-for data frequently is in the cache (i.e., there is a high hit rate for the cache). However, in instances where the sought-for data is frequently not found in the cache (i.e., there is a low hit rate for the cache), this hierarchical cache approach results in additional delays as unfruitful searches are made of the caches before the processor resorts to accessing the data from external memory. Moreover, these higher level caches consume power regardless of their effective utilization, therefore causing an unnecessary power draw when such caches are underutilized.
Accordingly, a technique for minimizing the delays and power consumption caused by higher level caches would be advantageous.